- NOVELLUS SYSTEMS AND UALBANY NANOCOLLEGE LAUNCH $20 MILLION NANOELECTRONICS R&D PARTNERSHIP (Views:751, Saved 0 Time(s))
Leading Global Equipment Supplier to Locate Researchers and Cutting-Edge Tools
at CNSE’s Albany NanoTech to Support Development of Sub-22nm Chip Technologies
Albany, NY--July 13, 2009 – The College of Nanoscale Science and E... - NOVELLUS’ ADVANCED COPPER SEED TECHNOLOGY EXTENDS PVD INTERCONNECT TO SUB-2Xnm NODE (Views:737, Saved 0 Time(s))
Innovative Copper Seed Provides Bottom-up Fill That Reduces
The Pre-Electroplating Aspect Ratio
San Jose, Calif. – July 13, 2009 – Novellus Systems (NASDAQ:NVLS) announced today that it has developed an advanced Hollow Cathode Magne... - NOVELLUS’ PETER WOLTERS DIVISION DEVELOPS 22nm DOUBLE-SIDED SILICON WAFER POLISH PROCESS (Views:803, Saved 0 Time(s))
MicroLine® Technology Produces Extremely Flat Wafers to Meet Chip Manufacturing Lithography Requirements at 22nm And Beyond
San Jose, Calif. – June 23, 2009- To address the challenges of wafer polishing at future technology nodes, Peter... - NOVELLUS' ULTRA LOW DIELECTRIC CONSTANT MATERIALS ENABLE 32nm DEVICE INTEGRATION (Views:810, Saved 0 Time(s))
New Dense ULK Materials More Reliable, Easier to
Integrate than Porous Alternatives
San Jose, Calif. – June 18, 2009 – Novellus (NASDAQ: NVLS) has developed Dense ultra low dielectric constant (ULK) films that provide more reliable ... - New IBM ILOG Products Help Customers React Faster to Business Challenges (Views:749, Saved 0 Time(s))
Offerings Include Supply Chain Applications and Business Rule Management System Applications
SUNNYVALE, Calif. and PARIS – June 17, 2009 – ILOG, an IBM Company, today announced new offerings across its business rule management and supply cha... - NOVELLUS’ SUB-45nm HDP GAPFILL PROCESS PROVIDES 3X REDUCTION IN MEDIAN DEFECT DENSITY (Views:631, Saved 0 Time(s))
SPEED® Max Process Has 50 Percent Fewer Out-Of-Control Particles Compared To Current Gapfill Technologies
San Jose, Calif. – June 4, 2009 - Novellus Systems (NASDAQ: NVLS) has developed a sub-45nm, in-situ chamber clean process on the S... - NOVELLUS’ HCM® IONX™ XL Ta(N) BARRIER TECHNOLOGY ENABLES 3X/2Xnm MEMORY TRANSITION TO COPPER (Views:758, Saved 0 Time(s))
Conformal HCM PVD Films Provide Robust Copper Barrier
As Compared To Conventional Planar PVD Technology
San Jose, Calif. – May 27, 2009 – Ten years after the introduction of copper metallization for logic device manufacturing, Physi... - NOVELLUS DEVELOPS RESIDUE-FREE, 3X/2Xnm HIGH DOSE IMPLANT STRIP PROCESS (Views:720, Saved 0 Time(s))
Innovative, CF4-Based Approach Eliminates Photoresist Popping
and Residues That Negatively Impact Yield
San Jose, Calif. – May 13, 2009 – As device performance requirements increase at the 3xnm technology node and beyond, the require... - NOVELLUS’ 32nm UV-ABSORBING DIELECTRIC FILMS KEY TO IMPROVED DEVICE RELIABILITY (Views:769, Saved 0 Time(s))
Dense ULK and Diffusion Barrier Stack Absorbs Order-of-Magnitude More UV Radiation
Than Porous Interconnect Alternatives
San Jose, Calif. – May 6, 2009 – In order for RC delay to continue to scale in accordance with the Internationa... - NOVELLUS' COOLFILL CVD PROCESS ADVANCES TUNGSTEN FILL FOR SUB-32nm HIGH ASPECT RATIO STRUCTURES (Views:804, Saved 0 Time(s))
San Jose, Calif. - April 16, 2009- As semiconductor devices scale to the 32nm technology node and beyond, shrinking contact and via dimensions make chemical vapor deposition (CVD) of tungsten more challenging. Increasing aspect ratios can lead to voids or... - NOVELLUS’ SUPPRESSION-ENHANCED FILL™ TECHNOLOGY PROVIDES DEFECT-FREE 32nm COPPER INTERCONNECTS (Views:658, Saved 0 Time(s))
Unique Hardware and Process Chemistry Extend Cu Manufacturing Capability
San Jose, Calif. – April 9, 2009 – Since the advent of copper damascene processing, achieving void-free fill of high aspect ratio interconnect features h... - NOVELLUS’ ULTRA-THIN DIELECTRIC DIFFUSION BARRIERS BOOST 32nm INTERCONNECT PERFORMANCE (Views:660, Saved 0 Time(s))
Low Risk Solution Enabled by Novellus Architecture
San Jose, Calif. – April 1, 2009 – In order to support the RC delay scaling required by the International Technology Roadmap for Semiconductors (ITRS), process designers have focused ... - Novellus' Innovative 32 nm Dielectric Technologies Enable Interconnect RC Delay Scaling (Views:732, Saved 0 Time(s))
Technology Package Delivers 5 Percent Lower keffective Without Complex Material Changes
San Jose, Calif. – March 18, 2009 – In order for device performance to keep pace with Moore’s Law, integrated circuit designers have had to ... - Tokyo Electron and Novellus Systems Announce Breakthrough Results and Collaboration on Copper Process Technology for 2Xnm and Beyond (Views:727, Saved 0 Time(s))
TOKYO, Japan and SAN JOSE, Calif. – December 1, 2008 – Tokyo Electron Ltd. (TEL) and Novellus Systems, Inc. (NASDAQ: NVLS) are pleased to announce the availability of an integrated copper interconnect solution for the 2Xnm generation and bey... - Novellus Ships 300th SABRE System, Marking 10 Years of Leadership in Copper Technology (Views:812, Saved 0 Time(s))
SAN JOSE, Calif. – September 23, 2008 – Novellus Systems, Inc. (NASDAQ: NVLS) today announced the shipment of its 300th SABRE® electrochemical deposition (ECD) system to a leading semiconductor manufacturer in Korea. The SABRE Extr...
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